In the fabrication of semiconductor devices, metal lines are often embedded in dielectric layers in a multilevel structure, particularly in the latter stage (“back end of the line” or “BEOL”) of the fabrication process. The last layer of metal lines (sometimes referred to in the art as the terminal via or TV layer) with metal pads formed thereon are fabricated by a process typically referred to as “far back end of line” or “FBEOL.” The pads and metal lines together provide last level interconnects from an IC chip to other system components. The majority of IC chips use aluminum (Al) to form the interconnects, but more recently copper (Cu) interconnects are used. The advantages of using Cu rather than Al interconnects include higher conductivity (with lower resistance), lower capacitive load, lower power consumption, less cross talk, fewer metal layers, and few potential manufacturing steps.
An IC chip containing copper interconnects may be electrically connected to a substrate or other electrical components by solder bumps, which are also commonly referred to as flip chip bonds. Solder bump technology (also known as flip chip technology in the art) provides higher density and higher performance connections. An example of solder bump technology is controlled-collapse chip connection (C4), in which solder bumps are provided on both the IC chip and the substrate, and the connection is established by aligning the solder bumps of the IC chip and the substrate and reflowing the solder to make the connection. In a typical C4 connection, a solder bump is formed by first depositing solder on a ball-limiting metallurgy (BLM), which is formed over a copper interconnect located in a substrate, followed by heating the solder to above its melting temperature, thereby causing reflow of the solder into a ball. The size and shape of the solder ball so formed is limited by the dimension of the BLM due to surface tension.
However, tin (Sn) contained in the solder bump may diffuse into the copper interconnect, and it typically interacts with Cu to form a brittle Cu/Sn intermetallic interface, which leads to disconnection of the copper interconnect from the solder bump. In order to prevent the solder from diffusing into the copper interconnect, at least one aluminum capping layer is provided between the solder bump and the copper interconnect. Further, additional diffusion barrier layers containing materials, such as titanium nitride or tantalum nitride, are provided between the aluminum capping layer and the copper interconnect, in order to prevent diffusion of copper into the aluminum capping layer. Fabrication of such an aluminum capping layer and associated diffusion barrier layers involves multiple processing steps, which significantly increase the manufacturing cost of IC chips.
There is therefore a continuing need for improved capping structures in the last level copper-to-C4 connections. Preferably, such improved capping structures: (1) provide good electrical connection between the last level copper interconnects and the C4 solder bumps, (2) eliminate or reduce Sn diffusion into the copper interconnects, and (3) can be fabricated by a simpler fabrication process at lower costs, in comparison with conventional aluminum-based capping structures.